Smart power component

ABSTRACT

A power component is proposed which reliably switches inductive loads and has a current detection element to detect the current through the inductive load. The component includes a protective element which is connected to the source terminals of the sense element and of the actuator. The protective element protects against parasitic effects between the sense element and the actuator.

FIELD OF THE INVENTION

The present invention relates to a power component.

BACKGROUND INFORMATION

Power components having an actuator which is adjacent to a measuringelement are already known in the form of SENSEFET transistors.

SUMMARY OF THE INVENTION

In contrast, the power component of the present invention has theadvantage that it ensures safe and reliable operation even with highcurrents through the actuator as well as protection against the risk offailure.

In SmartPower components such as SENSEFET transistors in particular (inDMOS design, for example) or in IGBT transistors having an integratedsense element, a reliable protection is ensured against overvoltange andbreakdowns between the sense cell and adjacent DMOS cell. In particularwhen employed as a high-side switch, critical operating conditions suchas, for example ground and/or battery separation, ISO pulses(interference pulses from the supply system) or with inductive loads orcable inductances can be withstood without risk of failure of the powercomponent. Moreover, it has proven to be advantageous that there is noadverse effect on the current detection by the sense element in normaloperation as a consequence of the arrangement provided. Moreover, thearrangement can be integrated monolithically.

If the arrangement prevents an activation of existing parasitic bipolartransistors, for example, by preventing the buildup of the basepotential, then the danger of a second breakdown with subsequent fusingis prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a SENSEFET transistor in cross-section.

FIG. 2 shows a first exemplary embodiment.

FIG. 3 shows a second exemplary embodiment.

FIG. 4 shows a third exemplary embodiment.

FIG. 5a shows a fourth exemplary embodiment.

FIG. 5b shows a fifth exemplary embodiment.

DETAILED DESCRIPTION

FIG. 1 shows a transistor having a sense element, in cross-section. Aweakly n-doped semiconductor layer is arranged on a p-doped substrate 1.Weakly p-doped regions 3 are arranged in semiconductor layer 2, thep-doped regions being separated from each other by regions ofsemiconductor layer 2. A strongly p-doped region 4 is arranged in thecenter of each of regions 3, the p-doped region extending from thesurface of the semiconductor component to a depth in which region 4 isalways directly in contact with semiconductor layer 2. Strongly n-dopedregions 5 are incorporated in the margins of strongly p-doped regions 4,each of strongly n-doped regions 5 extending somewhat into weaklyp-doped region 3 at the edge of each of the strongly p-doped regions 4.A weakly p-doped region 30 is 25 also incorporated in semiconductorlayer 2 by analogy to region 5. By analogy to region 4, a stronglyp-doped region 40 is incorporated in weakly p-doped region 30; byanalogy to strongly n-doped regions 5, strongly n-doped region 29 isincorporated in strongly p-doped region 40. Gate electrodes 6, insulatedfrom the semiconductor layer by an insulating layer, are arranged abovethe regions of semiconductor layer 2 which extend to the surface of thesemiconductor component. Gate electrodes 6 are electrically connectedwith each other and can be electrically contacted via gate terminal 11.Strongly n-doped regions 5 and strongly p-doped regions 4 areelectrically connected with each other and can be jointly electricallycontacted via source/load terminal 10. Regions 40 and 29 are alsoelectrically connected and can be electrically contacted via senseterminal 12. Oxide layers and necessary metallic coatings on the surfaceof the semiconductor component are not shown in FIG. 1 for reasons ofsimplicity of presentation. If the component of FIG. 1 is designed as aDMOS power transistor, a strongly n-doped drain region, for example, isincorporated in weakly n-doped semiconductor layer 2. This drain regionis not shown in FIG. 1. This drain region can be electrically contactedvia a front drain terminal which is also not illustrated and in additionto load terminal 10, gate terminal 11 and sense terminal 12, representsthe fourth terminal of a SENSEFET transistor.

The p-region 3, p-region 30 and the region of semiconductor layer 2lying between the two p-regions form a parasitic PMOS transistor. At agate potential which is lower than the potential at sense terminal 12,this parasitic PMOS transistor has a threshold voltage between sourceterminal 10 and sense terminal 12 which is, for example, 4 volts. Ifregion 30 which represents the source region of the PMOS transistor isthen in contact with a potential which is at least 4 volts higher thanthe potential of the p-region, a parasitic p channel is activated insemiconductor layer 2. The parasitic PMOS transistor shifts current intoregion 3 of the adjacent DMOS cell which functions simultaneously as thebase of a vertical npn bipolar transistor. This parasitic npn transistoris formed by regions 5, 3/4 and semiconductor layer 2. In normaloperating conditions, switching through this parasitic npn bipolartransistor by a short-circuit between the strongly n-doped region 5 andstrongly p-doped region 4 is effectively prevented. The current of theparasitic PMOS transistor, however, allows the potential to build up inthe base region of the parasitic bipolar transistor so that the npnbipolar transistor is activated and there exists the danger of a secondbreakdown with fusion.

FIG. 2 shows a SENSEFET transistor 41, 42, a sense element 41 and anactuator 42 which, for example, is also constructed using DMOStechnology. The gate electrodes of sense element 41 and actuator 42 areconnected with a control circuit 47 which in turn is connected to thepower supply via both ground terminal 45 and voltage source 46.

Voltage source 46 is also connected to the drain terminals of the senseelement and actuator. An analysis circuit 49 is connected between ground45 and the source terminal of sense element 41. An inductive load 50 isconnected between source terminal 10 of actuator 42 and ground 45. Aprotective diode 48 is connected between source terminal 10 of actuator42 and the source terminal of sense element 41, the negative pole of theprotective diode being connected to source terminal 10 of actuator 42.

(Externally controllable) control circuit 47 controls the currentthrough actuator 42. Analysis circuit 49 evaluates the current throughsense element 41 which functions as a current detection element.Depending on the application, analysis circuit 49 is connected to otherelectronic circuits or to control circuit 47 in order to make theinformation concerning the size of the load current through actuator 42available to the other circuit components and to control circuit 47. Ifa ground separation or a voltage source separation occurs at inductiveload 50, the potential of source terminal 10 becomes negative due to themagnetic induction. As a result, protective diode 48 becomes conductivewhich guarantees that the source terminal of sense element 41 has apotential which is only a forward voltage higher than the potential ofsource terminal 10. This effectively prevents the parasitic PMOStransistor from being activated. In normal operation, however, the diodedoes not influence the function of sense element 41 since in normaloperation, protective element 48 is switched in reverse direction.

FIG. 3 shows an additional exemplary embodiment in which the samecomponents are identified with the same reference symbols as in FIG. 2and are not described again.

Instead of protective diode 48 in FIG. 2, a PMOS transistor 480 isconnected to the source terminals of sense element 41 and actuator 42,the transistor being connected as a diode in such a way that withnegative potential of source terminal 10 of actuator 42, the PMOStransistor is switched through.

FIG. 4 shows an additional exemplary embodiment in which a suppressorcircuit 490 is arranged instead of protective element 48. Thissuppressor circuit 490 has an NMOS transistor 62, a first resistor 63and a second resistor 64. First resistor 63 is connected to the sourceterminal of actuator 42. First resistor 63 is also connected with secondresistor 64. Second resistor 64 is connected to ground 45. The first andsecond resistors are connected to the gate electrode of NMOS transistor62. The source terminal of transistor 62 is connected to source terminal20 of actuator 42. The drain terminal of transistor 62 is connected tothe source terminal of sense element 41.

NMOS transistor 62 switches through if actuator 42 has a negative sourcepotential. The amount of the negative potential at which NMOS transistor62 switches through can be adjusted via the resistance values of firstresistor 63 and second resistor 64.

FIG. 5a shows a cross-section of a component according to FIG. 1 with anintegrated protective diode 48. The same reference symbols as in FIG. 1are not described here once more. Protective diode 48 has a weaklyp-doped region 72 incorporated in semiconductor layer 2, a stronglyp-doped region 71 being incorporated in turn in p-doped region 72 whichsurrounds p-doped region 71. A strongly n-doped region 70 is in turnincorporated in strongly 10 p-doped region 71. Strongly n-doped region70 is electrically connected to source terminal 10; strongly p-dopedregion 71 is connected to sense terminal 12. Similar to FIG. 1,electrical insulating layers and metal coatings have been left out ofthe drawing for simplification of presentation. This also explains, forexample, the stage of the right-hand one of the three gate electrodes 6shown which is underlaid with an insulating layer. FIG. 5b shows a powercomponent according to FIG. 1 with a protective element 480 designed asa PMOS transistor. Protective element 480, which is arranged in thevicinity of the sense element, has two weakly p-doped regions 76 and 79incorporated in semiconductor layer 2, strongly p-doped regions 77 and79 being incorporated in turn in weakly p-doped regions 76 and 78, thestrongly p-doped regions completely penetrating p-doped regions 76 and78 and being in direct contact with semiconductor layer 2. Gateelectrode 75 of protective element 480 is connected to source terminal10; strongly p-doped region 77 is connected to sense terminal 12 andstrongly p-doped region 79 is, like gate electrode 75, connected tosource terminal 10.

FIGS. 5a and b show simple implementations of the circuits according toFIGS. 2 and 3, respectively. No additional expense is necessary toimplement protective elements 48 and 480 since regions 71, 72, 76, 77,78 and 79 can be produced together with the semiconductor regionsnecessary for the actuator and the sense element. Of course, protectiveelements 48 and 480 can also be used in back-contacted components, i.e.,vertical power components or even IGBT components.

What is claimed is:
 1. A power component, comprising: an actuator; ameasuring element to perform current detection, and being adjacent tothe actuator; a first source terminal for the actuator; a second sourceterminal for the measuring element; a power supply; a ground terminal; avoltage source connected to the first source terminal and the secondsource terminal; an inductive load arranged between the first sourceterminal and the ground terminal; a control circuit to connect themeasuring element and the actuator and to control a current runningthrough the actuator, and being connected to the power supply via theground terminal and the voltage source; an analysis circuit to evaluatea current running through the measuring element and to make informationconcerning a size of the current running through actuator available tothe control circuit, and being connected to the control circuit andarranged between the ground terminal and the second source terminal; andan arrangement for protecting against a parasitic current and beingconnected between the first source terminal and the second sourceterminal, the arrangement for protecting being conductive when anegative potential is present at the first source terminal.
 2. Thecomponent according to claim 1, further comprising: a semiconductorlayer of a first conductivity type; a first region of a secondconductivity type embedded in the semiconductor layer; a second regionof the second conductivity type embedded in the semiconductor layer andbeing arranged adjacent to and separate from the first region; and astructure including at least one of: at least one third region embeddedin the first region, and at least one fourth region embedded in thesecond region, wherein: the first region is connected to the firstsource terminal, the second region is connected to the second sourceterminal, the first region, the second region, and a region of thesemiconductor layer between the first region and the second region forma parasitic MOS transistor, and the arrangement for protecting preventsa voltage present between the first source terminal and the secondsource terminal from attaining a threshold value that would result in anactivation of the parasitic MOS transistor.
 3. The component accordingto claim 2, wherein: the first region, the at least one third region,and a region of the semiconductor layer lying between the first regionand the at least one third region form a parasitic bipolar transistor,the first region is short-circuited with the at least one third regionand forms a base of the parasitic bipolar transistor, and thearrangement for protecting prevents an activation of the parasiticbipolar transistor.
 4. The component according to claim 2, wherein: thearrangement for protecting is blocked as long as the threshold value isnot reached.
 5. The component according to claim 1, wherein: thearrangement for protecting includes a Zener diode, an anode of the Zenerdiode is connected to the second source terminal, and a cathode of theZener diode is connected to the first source terminal.
 6. The componentaccording to claim 1, wherein: the arrangement for protecting includesan MOS transistor that is connected as a diode to the first sourceterminal and the second source terminal, such that when the negativepotential is present at the first source terminal the MOS transistor isswitched through.
 7. The component according to claim 1, wherein: thearrangement for protecting includes a protective circuit having at leastone resistor with a resistance enabling an adjustment of an amount ofthe negative potential at the first source terminal to activate asuppressor circuit .
 8. The component according to claim 1, wherein: thecomponent is designed as an MOS component.
 9. The component according toclaim 1, wherein: the component is designed as an IGBT component. 10.The component according to claim 1, wherein: the arrangement forprotecting is monolithically integrated with the actuator and themeasuring element.
 11. The component according to claim 1, wherein: thecomponent is capable of switching an inductive load without risk offailure.
 12. The component according to claim 11, wherein: the componentswitches the inductive load as a high-side switch.
 13. The componentaccording to claim 1, wherein: the arrangement for protecting ensures anundisturbed operation of the measuring element as long as thearrangement for protecting is not activated.